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UID:69da744e150c4@www.leap-up.com
DTSTAMP:20260411T181822Z
DTSTART:20211006T130000Z
DTEND:20211006T140000Z
SUMMARY:Challenges and Solutions to Analog Integrated Design Efficiency
DESCRIPTION:Analog/mixed-signal IC design is a critical challenge for ASIC development with tight specs and tapeout schedules that are not easy to meet. Therefore\, we continuously identify and work on design concepts and tools that support the designers in both design efficiency and risk management. In this webinar\, we will give you an insight into some of these solutions.
LOCATION:Fraunhofer IIS/EAS\, Dresden
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