Events
Lorem ipsum dolor sit amet, consectetur adipiscing elit. Nunc vulputate libero et velit interdum, ac aliquet odio mattis.
#read
Intelligent IP for automated A/MS IC design and technology porting
Datum & Uhrzeit
- von
- 01.07.202015:00
- bis
- 01.07.202016:00
- Dauer
- 1Stunde
Ort
- Stadt
- online
Kontakt
- Name
- Frau Sandra KundelFraunhofer-Institut für Integrierte Schaltungen IIS, Institutsteil Entwicklung Adaptiver Systeme EAS
- Telefon
- +49 351 4640-809
- fnaqen.xhaqry@rnf.vvf.senhaubsre.qr
Learn how our solution on analog automation can support your IC design flow to meet tapeouts in time. Whether your design phase should be accelerated, design migration eased, or your custom problem be automated–with intelligent IPs, Fraunhofer IIS/EAS offers an applied solution for a new era of analog integrated circuit design.