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Reusable Analog IP – Make Your IP Intelligent with Intelligent IP

Name: Reusable Analog IP – Make Your IP Intelligent with Intelligent IP
Start: 2022-05-04T16:00:00+02:00
End: 2022-05-04T17:00:00+02:00
Location: Fraunhofer IIS/EAS

Online seminar
Virtual

download .ICS file

Date & Time

from: 04/05/202216:00 pm
until: 04/05/202217:00 pm
duration: 1hour

Location

place: Fraunhofer IIS/EAS
address: Münchner Straße
city: 01187, Dresden Deutschland

Contact

Last name: Ms. Dr. Katja Lohmann-Schwitale
Fraunhofer IIS/EAS
phone: +49 351 45691 154
email: xngwn.ybuznaa-fpujvgnyr@rnf.vvf.senhaubsre.qr

Analog/mixed-signal IC design is a critical challenge for ASIC development with tight specs and tapeout schedules that are not easy to meet. Especially when targeting various applications or multiple PDKs, initial efforts, design time, and risks increase. In this webinar, we will give you an insight into approaches to ease IP reuse across both PDKs and specifications by means of analog automation.

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