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Reusable Analog IP – Make Your IP Intelligent with Intelligent IP

Date & Time

from
15/02/202316:00 pm
until
15/02/202317:00 pm
duration
1hour

Location

place
Fraunhofer IIS/EAS
city
Dresden Germany

Contact

Last name
Ms. - Marie Noack
Fraunhofer IIS/EAS
email

Designing analog/mixed-signal ICs is a major challenge for ASIC development with tight specifications and tapeout schedules that are not easy to meet. Therefore, we are continuously working on concepts and automated design tools that help designers with both design efficiency and risk management. In this webinar we will give you an insight into some of these solutions and how you can benefit from our solutions via licensing or as part of contract development of analog automation.

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