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Challenges and Solutions to Analog Integrated Design Efficiency

Name: Challenges and Solutions to Analog Integrated Design Efficiency
Start: 2021-10-06T13:00:00+02:00
End: 2021-10-06T14:00:00+02:00
Location: Fraunhofer IIS/EAS

Online seminar

download .ICS file

Date & Time

from: 06/10/202113:00 pm
until: 06/10/202114:00 pm
duration: 1hour

Location

place: Fraunhofer IIS/EAS
city: Dresden Deutschland

Contact

Last name: Ms. Dr. Katja Lohmann-Schwitale
Fraunhofer IIS/EAS
phone: +49 351 4640 726
email: xngwn.ybuznaa-fpujvgnyr@rnf.vvf.senhaubsre.qr

Analog/mixed-signal IC design is a critical challenge for ASIC development with tight specs and tapeout schedules that are not easy to meet. Therefore, we continuously identify and work on design concepts and tools that support the designers in both design efficiency and risk management. In this webinar, we will give you an insight into some of these solutions.

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